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Here you will find the latest news and activities for the Austin CPMT chapter.
Upcoming events
7th meeting of the IEEE's CPMT-Chapter in Austin
Location:
Freescale Semiconductor,
Long Canyon Conference Room in Bldg C-Lobby
7700 W. Parmer Lane, Austin, TX 78729
When:
Thursday, April 23, 2008 Time: 6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker:
Dr. Madhavan Swaminathan,
Deputy Director, Microsystems Packaging Research Center
Georgia Institute of Technology, Atlanta
Topic: Power Integrity Modeling and Design for Semiconductor and Systems
Power represents the major bottleneck in modern semiconductors and systems. With transistor scaling, Moore’s law has enabled the integration of millions of transistors within an integrated circuit over the last two decades. With lower gate capacitance and lower voltage, faster transistors have resulted from one computer generation to the next. However, increased transistor integration has resulted in an increase in the current supplied to the integrated circuit, thereby increasing power. Managing the transient current supplied to the integrated circuit at gigahertz frequencies is one of the biggest challenges faced by the semiconductor industry. With lowering of the supply voltage to the transistors, dynamic variations in the power supply due to current transients is becoming a major bottleneck. The dynamic variation of the supply voltage, also called power supply noise, delta I noise, or simultaneous switching noise, is the subject of this seminar.
Managing power integrity is the process by which the variations on the power supply of the transistors can be maintained within a specified tolerance value. Noise on the power supply can have a direct influence on the speed of an integrated circuit, and hence supplying clean power is a very important element in the design of a computer system.
A power distribution network consists of interconnections in the chip, package, and board that include decoupling capacitors, ferrite beads, DC–DC converters, and other components. Both the package and board form a very critical part of the power distribution network and have a major influence on power integrity of the entire system. The focus of this seminar is on power integrity in packages and boards.
Modeling is a very critical part of power integrity design. Unlike Signal Integrity, modeling Power Integrity is not straight forward. Moreover, Signal Integrity and Power Integrity are inter-related and their influence on each other cannot be ignored. This seminar covers various elements of Power Integrity modeling with focus on real world applications..
The seminar will be structured around the recently published book entitled “Power Integrity Modeling and Design for Semiconductors and Systems”, ISBN:0_13_615206_6, Prentice Hall, Nov. 2007 by the speaker. The book comes with several practical examples related to power integrity modeling that can be reproduced using the free software that can be downloaded from www.sopworx.com. Attendees interested in purchasing the book will also obtain a special discount from Prentice Hall.
Madhavan Swaminathan is the Joseph M. Pettit Professor of Electronics in the School of Electrical and Computer Engineering and Deputy Director of the Microsystems Packaging Research Center, Georgia Tech. He is the co-founder of Jacket Micro Devices, a leader in integrated RF modules and substrates for wireless applications (www.jacketmicro.com) and SoPWorX, an EDA company specializing in CAD software for System on Package applications (www.sopworx.com). Prior to joining Georgia Tech, he was with IBM working on packaging for supercomputers. He is the author of more than 300 journal and conference publications, holds 15 patents, is the author of two books entitled “Power Integrity Modeling and Design for Semiconductors and Systems”, ISBN 0_13_615206_6. Prentice Hall, Nov 2007 and “Introduction to System on Package”, MCGraw Hill, Mar. 2008. He has been honored as an IEEE Fellow for his work on power delivery for digital and mixed signal systems. He received his M.S and PhD in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.
7:30 PM --- Meeting ends
Please invite others (CPMT member or Non-Member) interested in this Chapter.
PLEASE RSVP Om for joining the meeting by April 21, 2008
6th meeting of the IEEE's CPMT-Chapter in Austin
Location:
Freescale Semiconductor,
Long Canyon Conference Room in Bldg C-Lobby
7700 W. Parmer Lane, Austin, TX 78729
When:
Thursday, April 3, 2008 Time: 6:00 PM - 7:30 PM
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker: Dr. Brian Young , Texas Instruments
Topic: Signal and Power Integrity Design of Packages for High-End ASICs
ABSTRACT:
First-pass success of a new ASIC in a new application requires that the signal and power integrity meet their budgets. This in turn requires that the ASIC is properly designed to enable its successful integration and that the system is properly designed to enable the successful operation of the ASIC.
A successful ASIC design flow must be comprehensive and self-consistent while taking practical steps to limit complexity, computational intensity, and manpower. Reasonable assumptions and approximations are required. Integration with existing tool flows and organizational structures is required.
The presentation covers one way to implement a high-volume ASIC packaging design flow covering a broad spectrum of applications. In this presentation, the packaging domain covers the package substrate and its design, PCB design, circuit selection and operation, power demands, and generally any aspect of the design that affects power and signal integrity.
Brian Young received the BSEE from Texas A&M University, the MSEE from the University of Illinois, and the PhD from the University of Texas. Between 1988 and 2002, he was with Texas A&M University, Hughes Aircraft Company, and Motorola working in various areas of microwave and digital circuit and package design. Since 2002, he has been with Texas Instruments in circuit design and then package design. He is currently the package design manager for the ASIC product group. He was an Associate Editor for the IEEE Transactions on Advanced Packaging from 2001 to 2003. He is the author of the book “Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages” and has authored or co-authored 27 papers and conference publications, and he holds 7 patents. He is a registered professional engineer in the state of Texas.
7:30 PM --- Meeting ends
Please invite others (CPMT member or Non-Member) interested in this Chapter.
PLEASE RSVP Om for joining the meeting by April 1, 2008
Previous: Fifth meeting of the IEEE's CPMT-Chapter in Austin
Location:
Freescale Semiconductor,
Long Canyon Conference Room in Bldg C-Lobby
7700 W. Parmer Lane, Austin, TX 78729
When:
Thursday, February 7th , 2007 Time: 6:00 PM - 7:30 PM
6:00 PM to 6: 15 PM --- Social with Food & Drinks
6:15 - 6:30 PM - CPMT Chapter in Austin Officers Re-election for 2008 (to fulfill the procedural requirement of IEEE-CTS guidance)
6:30 - 7:30 -- Presentation by the Invited Speaker - Dr. Byron Krauter, IBM Systems & Technology Group
Inductance Models
The successful design and analysis of high performance packaging requires a thorough understanding of the inductive effects that pertain to packaging interconnects and power delivery systems. In addition, the key to understanding these inductive effects starts with a thorough understanding of inductance models. This talk begins with a basic review of inductance and proceeds to the various inductance model formulations: 2D and 3D partial inductances, loop inductances, frequency dependent models and finally sparse inductances models including truncated inverse inductance models. Physical insights are provided along the way including one that may stop you from ever again twisting and curling your right hand in front of your face.
Byron Krauter received the B.S. degree in physics and mathematics and the M.S. degree in electrical engineering from the University of Nebraska, Lincoln, in 1976 and 1978, respectively. He received a Ph.D. in electrical engineering from the University of Texas at Austin, in 1995. He has been with IBM since 1979 and is presently developing extraction tools for packaging signal integrity and power distribution. His work at IBM has ranged from device design to circuit and chip design to package design to CAD tool development for chip and package analysis. His research interests include sparse boundary element method (BEM) techniques for packaging and interconnect analysis.
