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Here you will find the latest news and activities for the Austin CPMT chapter.
Upcoming events:
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I invite you all for the 14th meeting of the IEEE's CPMT-Chapter in Austin .
Location:
Freescale Semiconductor
Round Up Conference Room in Bldg B
7700 W. Parmer Lane, Austin, TX 78729
When:
Thursday, October 1, 2009
Time:
6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
--Welcome of the guests and the Speaker
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker: Dr. Ali Akbar Merrikh
Senior System Designer, Thermo-Mechanical Engineering Team, AMD
Topic: LOW-PROFILE CHIPSET MICROPROCESSOR HEATSINK OPTIMIZATION FOR SERVER FORM FACTORS
ABSTRACT
We present a methodology for optimizing footprint, metal mass, and thermal performance of an aluminum-extruded heatsink for cooling chipset microprocessors in server form factors. We base the analysis on predefined volume flow rate of air at a constant temperature assumed available upstream of the package. The front-to-back cooling assumption covers the worst-case ambient conditions, typical of chipset boundary condition in servers. We present studies covering a range of heatsink footprints to compare and minimize the heatsink footprint, at the same time satisfying thermal specification of the chipset microprocessor. The study also focuses on the system-level assessment of the optimum 60×40 mm2 footprint and corner cases by studying the effect of motherboard thermal conductivity as well as blockages on the heatsink case-to-ambient thermal resistance.
Biography of Dr. Ali Akbar Merrikh
Ali Akbar Merrikh received his bachelors and masters degrees in Mechanical engineering from Eastern Mediterranean University in Turkey. He received his Ph.D in Mechanical Engineering from the Southern Methodist University at Dallas, Texas in May 2004. Ali's dissertation covered understanding the two-phase blood flow and gas transport mechanism in the pulmonary micro-capillaries.
Ali joined Advanced Micro Devices as a senior systems design engineer in June 2006. He has been a part of the AMD's thermo-mechanical engineering team and since then he has been designing thermal solution for the next generation AMD products.
He has published three book chapters and thirty two articles within the last eight years. He was awarded Young Engineer of the Year by the ASME North Texas section in 2005. He has also served as the VP of the ASME Central Texas Section. He has been a member of the ASME (American Society for Mechanical Engineers), TSPE (Texas Society for Professional Engineers), and APS (American Physiological Society).
7:30 PM --- Meeting ends
Please invite others (CPMT member or Non-Member) interested in this meeting.
PLEASE RSVP me for joining the meeting by September 29, 2009
Regards.
Om
Om P. Mandhana, PhD
Chair, IEEE-CPMT Chapter in Austin
Technical Solutions Organization
Freescale Semiconductor, Austin, TX
(512)996-6063
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I invite you all for the I invite you all for the 13th meeting of the IEEE's CPMT-Chapter in Austin .
Location: Freescale Semiconductor
Round Up Conference Room in Bldg B
7700 W. Parmer Lane, Austin, TX 78729
When: Thursday, September 3, 2009
Time: 6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
--Welcome of the guests and the Speaker
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker: Sam Chitwood,
Manager, Field Applications Engineering Sigrity Inc
Topic: S-parameter Modeling for Signal and Power Distribution System Analysis
ABSTRACT
EDA simulation tools allow complex physical structures to be analyzed with S-parameter “black-box” models. Proper understanding of basic concepts, such as “Ports” and “Reference”, is key to successful analysis. This presentation will discuss how S-parameter models capture the behavior of non-ideal power, signal and ground structures for simultaneous switching noise (SSN) analysis, how S-parameters are extracted, and how to use S-parameter models in SPICE circuit-level simulations. Examples of power distribution system modeling and SSN simulations will be shown.
Biography of Mr. Sam Chitwood
Sam Chitwood is the Field Applications Engineering manager for Sigrity, Inc. Over the past six years with Sigrity, he has specialized in IC package and PCB modeling, power integrity analysis, and decoupling capacitor optimization. Before joining Sigrity, he was a signal and power integrity engineer for Dell Computer’s server division. He holds BS and MS EE degrees from Georgia Institute of Technology.7:30 PM --- Meeting ends
Please invite others (CPMT member or Non-Member) interested in this meeting.
PLEASE RSVP me for joining the meeting by September 1, 2009
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12th meeting of the IEEE's CPMT-Chapter in Austin .
Location: Freescale Semiconductor
Round Up Conference Room in Bldg B
7700 W. Parmer Lane, Austin, TX 78729
When: Thursday, August 6, 2009
Time: 6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
--Welcome of the guests and the Speaker
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker: Dr. M. Baris Dogruoz
Senior Product Specialist, ANSYS Inc
Topic: Advances in Thermal Modeling of Electronic Packages and Printed Circuit Boards
ABSTRACT
A printed circuit board or a substrate in an electronic package is generally a multi-layered structure made of dielectric material and several layers of traces and vias. Carrying out comprehensive numerical simulations on PCB's and electronic packages including meshed trace and via geometries for each of the layers is impractical. The effects of the trace and via geometry can accurately be included in the physical model by importing electronics computer aided-design (ECAD) data comprising the trace and via layouts and subsequently computing the locally varying orthotropic thermal conductivity values. Then, the spatially varying thermal conductivity information can be utilized in numerical simulations with a minimal increase in the overall computational cost. In addition, increases in PCB component densities will augment current densities thus leading to hot spots because of Joule heating. Therefore, it is crucial to account for the heating due to the high current-carrying traces in thermal simulations. In this talk, we will discuss both the trace layer non-homogeneity and Joule heating effects at the component and board level thermal simulations. Comparisons will be made with conventional modeling techniques whenever needed. We will see that there are considerable differences in the location of the hot spots and temperature values between different methods.
Biography of Dr. M. Baris Dogruoz
Dr. Dogruoz (Baris) is a senior thermofluids specialist at Ansys Inc. He received his Ph.D. degree in mechanical engineering from the University of Arizona in 2005. Upon his graduation, he joined Fluent Inc. / ICE Division as a special operations engineer. His research interests include modeling and experimentation in wall-bounded turbulent flows and heat transfer, micro/meso scale heat transfer, synthetic/impinging jets, air/liquid/spray cooling in electronics and intelligent material systems and structures.
7:30 PM --- Meeting ends
Please invite others (CPMT member or Non-Member) interested in this meeting.
PLEASE RSVP me for joining the meeting by August 2, 2009
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I invite you all for the 11th meeting of the IEEE's CPMT-Chapter in Austin .
Location: Freescale Semiconductor
Long Canyon Conference Room A in Bldg C-Lobby
7700 W. Parmer Lane, Austin, TX 78729
When: Thursday, June 4, 2009
Time: 6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
--Welcome of the guests and the Speaker -- By Om P. Mandhana (Chair, CPMT Chapter in Austin)
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker: Glenn G. Daves
Director of Packaging Solutions Development at Freescale Semiconductor
Topic: Packaging Development and Market Alignment
ABSTRACT
As with all successful development activity, evolving market requirements are the primary driver of new packaging technologies and products. However, the interplay of competing requirements and constrained schedules often makes market alignment a complex undertaking. To better explore these issues, examples are presented of market requirements and the packages and package technologies that resulted from the alignment process.
Biography of Glenn Daves
Glenn G. Daves is Director of Packaging Solutions Development at Freescale Semiconductor, responsible for research, development, and design of Freescale’s semiconductor packaging product and technology portfolio. This portfolio spans the range from low pin count molded wirebond packages, to high pin count flip chip, to specialty MEMs sensor and analog power packages. Prior to Freescale, Glenn was at IBM Corporation where, in his most recent position, he led IBM's global packaging product and technology development. Prior to this position, Glenn held management and technical roles in project management, packaging and assembly development, test and burn-in engineering, and assembly manufacturing engineering. Glenn holds fifteen U.S. patents and has degrees from Brown University, the University of Illinois at Urbana-Champaign, and Alliance Theological Seminary.
7:30 PM --- Meeting ends
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IEEE’s CPMT- Chapter in Austin Presents an all-day Workshop on 3D Packaging
Friday, March 27, 2009, at
Freescale Semiconductor
Parmer Lane Auditorium in Bldg A
7700 W. Parmer Lane, Austin, TX 78729
THEME:
IEEE CPMT sponsored workshop on 3D packaging to increase awareness of this fast emerging technology. Today, the topic of 3D packaging is pervasive and gaining attention among all fields of packaging development. 3D technology continues to evolve and cost/ performance benefits continue to expand. The workshop will present expert presentations in the areas of electrical, thermal, mechanical, design processes, and system integration challenges and available solutions.
WHO SHOULD ATTEND?
This workshop is intended for technical leaders, scientists, engineers, educators, researchers, developers, and students in the area of 3D packaging design, integration and manufacturing.
REGISTRATION: $75 per person (click here to download word document registration form) Note: Receipts will be mailed within 5-10 business days.
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10th meeting of the IEEE's CPMT-Chapter in Austin .
Location:
Freescale Semiconductor
Long Canyon Conference Room in Bldg C-Lobby
7700 W. Parmer Lane, Austin, TX 78729
When:
Thursday, February 12, 2009
Time: 6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
--Welcome of the guests and the Speaker -- By Om P. Mandhana (Chair, CPMT Chapter in Austin)
--Speaker Introduction -- By Paul M Harvey (Technical Program-Co-Chair, CPMT Chapter in Austin)
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker:
Dr. Paul S. Ho
Director of the Laboratory for Interconnects and Packaging at The University of Texas at Austin
Topic: Packaging Effects on Mechanical Reliability of Cu/low k Interconnects
ABSTRACT
Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during assembly into a plastic flip-chip package. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. This presentation will summarize the experimental and modeling studies to investigate the chip-package interaction and its impact on low k interconnect reliability. First, the packaging induced deformation and stress at the chip level is analyzed using high-resolution moiré interferometry and compared with process-induced stresses during chip fabrication. Then results from 3D finite element analysis (FEA) based on a multilevel sub-modeling approach to investigate the chip-package interaction for low k interconnects will be presented. Packaging induced crack driving forces for relevant interfaces in Cu/low k structures are deduced and compared with corresponding interfaces in Cu/TEOS structures. The effect due to the solder and underfill materials on packaging reliability will be discussed. Then the effects of wiring layout and geometry on chip-package interaction and their impact on low k interconnect reliability will be examined.
Biography of Dr . Paul S. Ho
Dr. Paul S. Ho is the Director of the Laboratory for Interconnect and Packaging at The University of Texas at Austin. He received his Ph.D. degree in physics Rensselaer Polytechnic Institute. He joined the Materials Science and Engineering Department at Cornell University in 1966 and became an Associate Professor in 1972. In 1972, he joined the IBM T.J. Watson Research Center and has held a number of management positions. In 1985, he became Senior Manager of the Interface Science Department. In 1991, he joined the faculty at the University of Texas and was appointed the Cockrell Family Regents Chair in Materials Science and Engineering. His current research is in the areas of materials and processing science for interconnect and packaging applications.
7:30 PM --- Meeting ends
Concluding Remarks -- By Bhyrav Mutnury (Secretary, CPMT Chapter in Austin)
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9th meeting of the IEEE's CPMT-Chapter in Austin .
Location:
Freescale Semiconductor
Long Canyon Conference Room in Bldg C-Lobby
7700 W. Parmer Lane, Austin, TX 78729
When:
Monday, November 10, 2008
Time: 6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
Welcome of guests and Speaker -- By Om P. Mandhana (Chair, CPMT Chapter in Austin)
Speaker Introduction -- By Moises Cases (Technical Program-Chair, CPMT Chapter in Austin)
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker:
Dr. William(Bill) Chen
Senior Technical Advisor at ASE (US) Inc.
President of IEEE CPMT
Topic: Why Technology Roadmap Matters to You
ABSTRACT
In recent years, we have seen great strides in Assembly and Packaging Technologies. Our industry is experiencing a tremendous surge of innovations and inventions driven largely by the consumer market. We have seen a bifurcation of Moore law technology driving forces towards More Moore and More than Moore. Technology Roadmaps are used in industry to set the pace of internal development as well as alignment of requirements and capabilities in the supply chain. This talk will review the ITRS Assembly and Packaging Roadmap, and the major technology trends to come. We will discuss why the Technology Roadmap matters to the Electronic Packaging and Assembly Community in industry and academia.
Biography of Dr . William (Bill) Chen
William Chen (Bill) holds the position of Senior Technical Advisor at ASE (U.S.) Inc. Prior to joining the ASE Group, he was the Director and Principal Research Fellow at the Institute of Materials Research & Engineering (IMRE) in Singapore. He worked for over thirty three years in various R&D and management positions at IBM Corporation. He was elected to the IBM Academy of Technology. He is the co-chair of the International Technology Roadmap for Semiconductors (ITRS) Assembly and Packaging International Technical Working Group. He has been an associate editor of the IEEE/CPMT transactions, and ASME Journal of Electronic Packaging. He has published extensively in the fields of microelectronics packaging and mechanics of materials. He is the President of the IEEE Components Packaging and Manufacturing Technology Society (CPMT), the global professional society for Electronic Packaging professional. He has been elected a Fellow of IEEE and a Fellow of ASME.
He held adjunct faculty appointments at Cornell University, Binghamton University, University of Washington, and visiting faculty appointment at Hong Kong University of Science of Technology. He received his B.Sc. at University of London, M Sc at Brown University and PhD at Cornell University
7:30 PM --- Meeting ends
Concluding Remarks -- By Bhyrav Mutnury (Secretary, CPMT Chapter in Austin)
PLEASE RSVP me for joining the meeting by November 7, 2008:
Om P. Mandhana, PhD Chair, IEEE's CPMT-Chapter in Austin
Netwoking and Computing Systems GroupFreescale Semiconductor, Inc.,
Austin, TX(512)996-6063
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8th meeting of the IEEE's CPMT-Chapter in Austin
Location:
Freescale Semiconductor,
Long Canyon Conference Room in Bldg C-Lobby
7700 W. Parmer Lane, Austin, TX 78729
When:
Thursday, October 16, 2008 Time: 6:00 PM - 7:30 PM
Agenda for the meeting:
6:00 PM to 6:20 PM --- Social with Food & Drinks
6:20 PM - Meeting Starts
6:30 PM - Invited Speaker's Seminar Starts
Invited Speaker:
Dr. Hubert Harrer,
IBM Server and Technology Group, Boeblingen, Germany
Topic: Power Multichip Module Packaging and its Impact on Server Architecture and Operating Systems
The presentation compares the system packaging and technologies of IBM´s latest system z high end servers. Starting from the z900, the system design change towards a blade-like architecture will be explained. The latest system generation z10 has achieved a doubling of the multiprocessor performance compared to the z9 system by maximizing its CPU configuration in combination with increasing the speed of the interconnections.
The heart of a processor node consists always of a multi chip module (MCM) which contains the double core processor chip, the cache chips and the bus adaptors to the memory and the IO chips. This MCM technology is the key for the high bandwidths between processor chips and the cache chips. The glass ceramic module has accomplished this challenge within the 102 layers resulting in a total wiring length of 545m. The increase of bandwidth requirements for the packaging will be compared for the last generations. Also the complex board and card technology of the second level packaging will be discussed.
The cooling of the system is being done with a modular refrigeration unit (MRU), which cools the processor chips down to 45-55C. This low temperature ensures highest reliability and reduced leakage current of the chips. An air cooled backup mode at a lower frequency ensures that the system does not go down in case of an MRU fail. The MCM has been designed for a maximum power of 1650W.
The presentation will focus on the electrical design methodologies for high end servers like power delivery concepts, signal integrity methodologies and power integrity designs for delivering such high currents.
Dr. Harrer is a Senior Technical Staff Member (STSM) since 2002 working in the IBM Server and Technology Group. He received his Dipl.-Ing. degree in 1989 and his Ph.D. degree in 1992 from the Technical University of Munich. In 1993 he received a DFG research grant to work at the University of California at Berkeley in the paradigm of Cellular Neural Networks.
Since 1994 he has worked for IBM in the Boeblingen Packaging Department. In 1999 he was on international assignment at IBM Poughkeepsie, New York. He was leading the z900 MCM designs and is the technical lead for z-series CEC packaging designs since 2001. This includes the system z990, z9 and system z10 mainframe computers. His technical interests focus on packaging technology, high frequency designs and electrical analysis for first and second level packaging. He has published multiple papers and holds 7 patents in the area of packaging.
7:30 PM --- Meeting ends
